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EM MICROELECTRONIC - MARIN SA
V3020
Ultra Low Power 1-Bit 32 kHz RTC
Description
The V3020 is a low power CMOS real time clock. Data is transmitted serially as 4 address bits and 8 data bits, over one line of a standard parallel data bus. The device is accessed by chip select ( CS ) with read and write control
timing provided by either RD and WR pulse (Intel CPU) or DS with advanced R/ W (Motorola CPU). Data can also be transmitted over a conventional 3 wire serial interface having CLK, data I/O and strobe. The V3020 has no busy states and there is no danger of a clock update while accessing. Supply current is typically 390 nA at VDD = 3.0V. Battery operation is supported by complete functionality down to 1.2V. The oscillator is typically 0.3 ppm/V.
Features
Supply current typically 390 nA at 3V 50 ns access time with 50 pF load capacitance Fully operational from 1.2V to 5.5V No busy states or danger of a clock update while accessing Serial communication on one line of a standard parallel data bus or over a conventional 3 wire serial interface Interface compatible with both Intel and Motorola Seconds, minutes, hours, day of month, month, year, week day and week number in BCD format Leap year and week number correction Time set lock mode to prevent unauthorized setting of the current time or date Oscillator stability 0.3 ppm / volt No external capacitor needed Frequency measurement and test modes Temperature range: -40C to +85C On request extended temperature range, -40C to +125C Pin compatible with the V3021 TSSO8 and SO8 packages
Applications
Utility meters Battery operated and portable equipment Consumer electronics White/brown goods Pay phones Cash registers Personal computers Programmable controller systems Data loggers Automotive systems
Typical Operating Configuration
or R/
Pin Assignment
or
CPU
SO8
XI XO
Address Decoder
VDD
WR
V3020
CS
RD
CS
VSS
XI V3020 XO
I/O
Address Bus
RD WR I/O
Data Bus
TSSO8
WR RD
VDD XI XO
CS
RD WR
I/O
V3020
VSS
CS
RAM
Fig. 1 Copyright (c) 2005, EM Microelectronic-Marin SA 1
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V3020
Absolute Maximum Ratings
Parameter Maximum voltage at VDD Minimun voltage at VDD Maximum voltage at any signal pin Minimum voltage at any signal pin Maximum storage temperature Minimum storage temperature Electrostatic discharge maximum to MIL-STD-883C method 3015.7 with ref. to VSS Maximum soldering conditions Symbol VDDmax VDDmin
Vmax Vmin TSTOmax TSTOmin VSmax TSmax
Handling Procedures
Conditions VSS + 7.0V VSS - 0.3V
VDD + 0.3V VSS - 0.3V +150C -65C 1000V 250C x 10s
Table 1
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Parameter Symbol 1) Operating temperature TA Logic supply voltage VDD Supply voltage dv/dt (power-up & power-down) Decoupling capacitor Crystal Characteristics 2) Frequency f Load capacitance CL Series resistance RS
1)
Min -40 1.2
Typ 5.0
Max Unit +125 C 5.5 V 6 V/s nF kHz 12.5 pF 50 k Table 2
100 32.768 8.2 35
Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
7
2)
The maximum operating temperature is confirmed by sampling at initial device qualification. In production, all devices are tested at +85C. On request, devices tested at +125C can be supplied. See Fig. 5
Electrical Characteristics (standard temperature range)
VDD= 5.0V 10%, VSS = 0V and TA=-40 to +85C, unless otherwise specified Parameter Symbol Test Conditions Total static supply ISS All outputs open, all inputs at VDD VDD = 3.0V, address 0 = 0 TA = 0 to +70C Total static supply ISS All outputs open, all inputs at VDD VDD = 5V, address 0 = 0 TA = 0 to +70C Dynamic current ISS I/O to VSS through 1M RD = VSS, WR = VDD, CS = 4 MHz address 0 = 0, read all 0 Input / Output Input logic low VIL Input logic high VIH Output logic low VOL IOL = 4 mA Output logic high VOH IOH = 4 mA Input leakage IIN 0.0 < VIN < 5.0V Output tri-state leakage on I/O ITS CS high, and address 0, bit 0, low pin Oscillator Starting voltage VSTA Input capacitance on XI CIN TA = +25C Output capacitance on XO COUT TA = +25C Start-up time TSTA Frequency stability 1.5 VDD 5.5V, TA = +25C f/f Frequency Measurement Mode Current source on I/O pin IONF CS high, addr.0, bit 0, high pulsed on/off @ 256 Hz VI/O = 1V
Min
Typ 390
460
Max 600
490 800 600 300
Unit nA
nA nA nA A
1.0 3.5 0.4 2.4 0.1 0.1 1.2 13 9 1 0.3 10 25 1 1
V V V V A A V pF pF s ppm/V A
Table 3
0.5 60
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V3020
Electrical Characteristics (extended temperature range)
VDD= 5.0V 10%, VSS = 0V and TA=-40 to +125C, unless otherwise specified Parameter Symbol Test Conditions Total static supply ISS All outputs open, all inputs at VDD VDD = 3.0V, address 0 = 0 Total static supply ISS All outputs open, all inputs at VDD address 0 = 0 Dynamic current ISS I/O to VSS through 1M RD = VSS, WR = VDD, CS = 4 MHz address 0 = 0, read all 0 Input / Output Input logic low VIL Input logic high VIH Output logic low VOL IOL = 4 mA Output logic high VOH IOH = 4 mA Input leakage IIN 0.0 < VIN < 5.0V Output tri-state leakage on I/O ITS CS high, and address 0, bit 0, low pin Oscillator Starting voltage VSTA Supply voltage dV/dt (power+85C TA +125C up & power-down) Input capacitance on XI CIN TA = +25C Output capacitance on XO COUT TA = +25C Series resistance of the RS -40C TA +85C crystal 1) Start-up time TSTA TA = +125C 2.0 VDD 5.5V, TA = +25C Frequency stability f/f Frequency Measurement Mode Current source on I/O pin IONF CS high, addr.0, bit 0, high pulsed on/off @ 256 Hz VI/O = 1V
1)
Min
Typ
Max 4
7
300
Unit A
A
A
1.0 3.5 0.4 2.4 0.1 0.1 1.2 0.006 13 9 90 10 0.3 8 25 0.5 60 1 1
V V V V A A V V/s pF pF k s ppm/V A
Table 4
6
Analyses done at high temperature with crystal type Micro Crystal CX2V-02
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V3020
The V3020 will run slightly too fast, in order to allow the user to adjust the frequency, depending on the mean operating temperature. This is made since the crystal adjustment can only work by lowering the frequency with an added capacitor between XO and VSS. The printed circuit capacitance has also to be taken into consideration. The V3020 in DIL 8 package, running with an 8.2 pF crystal at room temperature, will be adjusted to better than 1s/day with a 6.8 pF capacitor.
Typical Standby Current at VDD = 3V
Fig. 3a
Typical Standby Current at VDD = 3V and Extended Temperature
Fig. 3b
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V3020
Typical Standby Current at VDD = 5.5V
Fig. 4a
Typical Standby Current at VDD = 5.5V and Extended Temperature
Fig. 4b
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V3020
Typical Frequency on I/O Pin
Typical drift for ideal 32'768 Hz quartz
Note: The trimming capacitor value must not exceed 15 pF. Greater values may disturb the oscillator function
Fig. 5
Quartz Characteristics
ppm F 2 (T - TO) 10% = -0.038 FO C2 F/FO = the ratio of the change in frequency to the nominal value expressed in ppm (it can be thought of as the frequency deviation at any temperature) the temperature of interest in C the turnover temperature (25 5C)
T TO
= =
To determine the clock error (accuracy) at a given temperature, add the frequency tolerance at 25C to the value obtained from the formula above.
Fig. 6
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V3020
Timing Characteristics (standard temperature range)
VSS= 0V and TA=-40 to +85C, unless otherwise specified Parameter Symbol Test Conditions Chip select duration RAM access time (note 1) Time between two transfers Rise time (note 2) Fall time (note 2) Data valid to Hi-impedance (note 3) Write data settle time (note 4) Data hold time (note 5) Advance write time Write pulse time (note 6) tCS tACC tW tR tF tDF tDW tDH tADW tWC Write cycle CLOAD = 50pF 500 10 10 15 80 120 20 500 200 200 200
Min. Max. VDD 2V
500 300
Min. Typ. Max. VDD = 5.0V 10%
50 50 100 10 10 15 50 25 10 50 30 200 200 40 60
Unit
ns ns ns ns ns ns ns ns ns ns
Table 4
Timing Characteristics (standard temperature range)
VSS= 0V and TA=-40 to +125C, unless otherwise specified Parameter Symbol Test Conditions Chip select duration RAM access time (note 1) Time between two transfers Rise time (note 2) Fall time (note 2) Data valid to Hi-impedance (note 3) Write data settle time (note 4) Data hold time (note 5) Advance write time Write pulse time (note 6) tCS tACC tW tR tF tDF tDW tDH tADW tWC Write cycle CLOAD = 50pF 500 10 10 15 80 120 20 500 100 100 200
Min. Max. VDD 2V
500 300
Min. Typ. Max. VDD = 5.0V 10%
60 50 120 10 10 15 50 25 15 60 30 100 100 50 60
Unit
ns ns ns ns ns ns ns ns ns ns
Table 4 ex.
Note 1: tACC starts from RD or CS , whichever activates last Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF Note 2: CS , RD , DS , WR and R/ W rise and fall times are specified by tR and tF Note 3: tDF starts from RD or CS , whichever deactivates first Note 4: tDW ends at WR or CS , whichever deactivates first Note 5: tDH starts from WR or CS , whichever deactivates first Note 6: tWC starts from WR or CS , whichever activates last and ends at WR or CS , whichever deactivates first
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V3020
Timing Waveforms
Read Timing for Intel ( RD and WR Pulse) and Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 7a
Write Timing for Intel ( RD and WR Pulse)
Fig. 7b
Write Timing for Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 7c
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V3020
Communication Cycles
Read Data Cycle for Intel ( RD and WR Pulse)
Fig. 8a
Read Data Cycle for Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 8b
Write Data Cycle for Intel ( RD and WR Pulse)
Fig. 8c
Write Data Cycle for Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 8d
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V3020
Address Command Cycle for Intel ( RD and WR Pulse) Address Command Cycle for Motorola ( DS (or RD pin tied to CS ) and R/ W )
Fig. 8e
Fig. 8f
Block Diagram
Fig. 9
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V3020
Pin Description
Pin SO8 TSSO8 1 3 2 4 3 5
4 5 6 7 8 6 7 8 1 2
Name
XI XO CS VSS I/O
Function
32 kHz crystal input 32 kHz crystal output Chip select input Ground supply Data input and output Intel RD , Motorola DS (or tie to CS ) Intel WR , Motorola R/ W Positive supply
Table 5
RD WR VDD
Address Command Cycle An address command cycle consists of just 4 address bits. The LSB, A0, is transmitted first (see Fig. 8e and 8f). On writing the fourth address bit, A3, the address will be decoded. If the address bits are recognized as one of the command codes E hex or F hex (see Table 6), then the communication cycle is terminated and the corresponding command is executed. Subsequent microprocessor writes to the V3020 begin another communication cycle with the first bit being interpreted as the address LSB, A0. Clock Configuration The V3020 has a reserved clock area and a user RAM area (see Fig. 9). The clock is not directly accessible, it is used for internal time keeping and contains the current time and data. The contents of the RAM is shown in Table 6, it contains a data space and an address command space. The data space is directly accessible. Addresses 0 and 1 contain status information (see Tables 7a and 7b), addresses 2 to 5, time data, and addresses 6 to 9, date data. The address command space is used to issue commands to the V3020. RAM Map Parameter Address Dec Hex Data Space 0 0 Status 0 1 1 Status 1 2 2 Seconds 3 3 Minutes 4 4 Hours 5 5 Day of month 6 6 Month 7 7 Year 8 8 Week day 9 9 Week number Address Command Space 14 E Copy_RAM_to_clock 15 F Copy_clock_to_RAM
Functional Description
Serial Communication The V3020 resides on the parallel data and address buses as a standard peripheral (see Fig.15 and 16). Address decoding provides an active low chip select ( CS ) to the device. For Intel compatible bus timing the
control signals RD and WR pulse and CS are used for a single bit read or write (see Fig. 7a and 7b). Two options exist for Motorola compatible bus timing. The first is to use the control signals DS with R/ W and CS , the second is to tie the RD input to CS and use the control signals R/ W and CS (see Fig. 7a and 7c). Data transfer is accomplished through a single input/output line (I/O). Any data bus line can be chosen. A conventional 3 wire serial interface can also be used to communicate with the V3020 (see Fig. 17).
BCD range
Communication Cycles The V3020 has 3 serial communication cycles. These are: 1) Read data cycle 2) Write data cycle 3) Address command cycle A communication cycle always begins by writing the 4 address bits, A0 to A3. A microprocessor read from the V3020 cannot begin a communication cycle. Read and write data cycles are similar and consist of 4 address bits and 8 data bits. The 4 address bits, A0 to A3, define the RAM location and the 8 data bits D0 and D7 provide the relevant information. An address command cycle consists of only 4 address bits. Read Data Cycle A read data cycle commences by writing the 4 RAM address bits (A3, A2, A1 and A0) to the V3020. The LSB, A0, is transmitted first (see Fig. 8a and 8b). Eight microprocessor reads from the V3020 will read the RAM data at this address, beginning with the LSB, D0. The th read data cycle finishes on reading the 8 data bit, D7. Write Data Cycle A write data cycle commences by writing the 4 RAM address bits (A3, A2, A1 and A0) to the V3020. The LSB, A0, is transmitted first (see Fig. 8c and 8d). Eight microprocessor writes to the V3020 will write the new RAM data. The LSB, D0, is loaded first. The write data th cycle finishes on writing the 8 data bit, D7.
00-59 00-59 00-23 01-31 01-12 00-99 01-07 00-52
Table 6
Commands Two commands are available (see Table 6). The Copy_RAM_to_clock command is used to set the current time and date in the clock and the Copy_clock_to_RAM command to copy the current time and date from the clock to the RAM. The Copy_RAM_to_clock command, address data E hex, causes the clock time and date to be overwritten by the time and date stored in the RAM at addresses 2 to 9. Address 1 is also cleared (see section "Time and Date Status Bits"). Prior to using this command, the desired time and date must be loaded into the RAM using write data cycles and the time set lock bit, address 0, bit 4, must be clear (see section "Time Set Lock").
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Status Information The RAM addresses 0 and 1 contain status control data for the V3020. The function of each ibt (0 and 7) within address locations 0 and 1 is shown in Table 7a and 7b respectively. Status Word
On first startup or whenever power has failed (VDD < 1.2V) the status register 0 and the clock must be initialized by software Having initialized the interface to expect the address bit A0, write 0 to status register 0, then set the clock (see section "Clock and Calendar"). Time and Date Status Bits There are time and date status bits at address 1 in the RAM. Upon executing a Copy_clock_to_RAM command, the time and date status bits in the RAM show which time and date parameters changed since the last time this command was used. A logic 1 in the seconds status bit (address1, bit 0) in the RAM indicates that the seconds location in the RAM (address 2) changed since the last Copy_clock_to_RAM command and thus need to be read. The seconds location must change before any other time or date location can change. If the seconds status bit is clear, then no time or date location changed since the last Copy_clock_to_RAM command and so the RAM need not to be read by software. Table 7b shows the seconds, minutes, hours, day of the month, month, year, week day, and week number status bit locations. They are set or cleared similar to the seconds location. It should be noted that if the minutes status bit is clear, then the seconds bit may be set, but ail other status bits are clear. Similarly with hours, the bits representing the units less than hours may have been set, but the bits for the higher units will be clear. This rule holds true for the week day or day of month locations also. The time and date status bits can be used to drive software routines which need to be executed every -second, -minute, -hour, -day of month / weekday, -month, -year, or -week. In this application it is necessary to poll the V3020 at least once every time interval used as it does not generate an interrupt. Upon executing a Copy _RAM_to_clock command, the time and date status bits in the RAM are cleared. Time Set Lock The time set lock control bit is located at address 0, bit 4 (see Table 7a). When set by software, the bit disables the Copy_RAM_to_clock command (see section "Commands".) A set bit prevents unauthorized overwriting of the current time and date in the clock. Clearing the time set lock bit by software will re-enable the Copy_RAM_to_clock command. On first startup or whenever power has failed (VDD < 1.2 V), the time set lock bit must be setup by software.
Status 0 - address 0 76543210
Read / Write bits Frequency Measurement Mode Reserved Test Mode 0 Test Mode 1 Time Set Lock Reserved Reserved Reserved
Table 7a
0 - inactive 1 - active
Status 1 - address 1 76543210
Read ONLY bits
01-
No change from last Copy_clock_to_RAM Change from last Copy_clock_to_RAM
Seconds Minutes Hours Day of month Month Year Week day Week number
Table 7b
Reset and Initialization Upon microprocessor recovery from a system reset, the V3020 must be initialized by software in order to guarantee that it is expecting a communication cycle (ie. the internal serial buffer is waiting for the address bit A0). Software can initialize the V3020 to expect a communication cycle by executing 8 microprocessor reads (see Fig. 10).
Initializing Access to the V3020
Fig. 10
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V3020
Reading the Current Time and Date
Send copy_clock_to_RAM addr. F hex
Setting the Current Time and Date
Write seconds, minutes, hours, day of month, week day, month, year and week number to the RAM
Read time and data status bits, addr. 1 Clear the time set lock bit, addr. 0, bit 4 Is the seconds status bit set, addr. 1, bit 0 No Send copy_RAM_to_clock command, addr. E hex
Yes Read seconds, addr. 2 Set the time set lock bit, addr. 0, bit 4
Is the minutes status bit set, addr. 1, bit 1
No
Fig. 12
Yes Read minutes, addr. 3
Similar for hours, day of month, week day, month, year and week number
Current time and date
Fig. 11
Clock and Calendar The Time and date addresses in the RAM (see Table 6) provide access to the seconds, minutes, hours, day of month, month, year, week day, and week number. These parameters have the ranges indicated on Table 6 and are in BCD format. If a parameter is found to be out of range, it will be cleared on its being next incremented. The V3020 incorporates leap year correction and week number calculation. The week number changes only at the incrementation of the day number from 7 to 1. If week th th th 52 day 7 falls on the 25 , 26 or 27 of December, then the week number will change to 0, otherwise it will be week 1. Week days are numbered from 1 to 7 with Monday as 1. Reading of the current time and date must be preceded by a Copy_clock_to_RAM command. The time and date status bits will indicate which time and date addresses changed since the last time the command was used (see Fig. 11). The time and date from the last Copy_clock_to_RAM command is held unchanged in the RAM, except when power (VDD) has failed totally. To change the current time and date in the clock, the desired time an date must first be written to the RAM, the time set lock bit cleared, and then a Copy_RAM_to_clock command sent (see Fig. 12). The time set lock bit can be used to prevent unauthorized setting of the clock.
Frequency Measurement Setting bit 0 at address 0 will put a pulsed current source (25 A) onto the I/O pin, when the device is not chip selected (ie. CS input high). The current source will be pulsed on/off at 256 Hz. The period for 0 ppm time keeping is 3.90625 ms. To measure the frequency signal on pin I/O, the data bus must be high impedance. The best way to ensure this is to hold the microprocessor and peripherals in reset mode while measuring the frequency. The clarity of the signal measured at pin I/O will depend on both the probe input impedance (typically 1 M) and the magnitude of the leakage current from other devices driving the line connected to pin I/O. If the signal measured is unclear, put a 200 k resistor from pin I/O to VSS. It should be noted that the magnitude of the current source (25 A) is not sufficient to drive the data bus line in case of any other device driving the line, but it is sufficient to take the line to a high logic level when the data bus is in high impedance. Use a crystal of nominal CL = 8.2 pF as specified in the section "Operating Conditions". The MX series from Microcrystal is recommended. The accuracy of the time keeping is dependent upon the frequency tolerance and the load capacitance of the crystal. 11.57 ppm corresponds to one second a day. Test From the various test features added to the V3020 some may be activated by the user. Table 7a shows the test mode b its. Table 8 shows the 3 available test modes and how they can be activated. Test mode 0 is activated by setting bit 2, address 0, and causes all time keeping to be accelerated by 32. Test mode 1 is activated by setting bit 3, address 0, and causes all the time and date locations, address 2 to address9, to be incremented in parallel at 1 Hz with no carry over (independent of each other). The third test mode combines the previous two resulting in parallel incrementing at 32 Hz.
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Test Modes Addr. 0 Addr. 0 bit 3 bit 2 0 0 0 1 1 1 0 1 Function Normal operation All time keeping accelerated by 32 Parallel increment of all time data at 1 Hz with no carry over Parallel increment of all time data at 32 Hz with no carry over
Table 8
Crystal Layout In order to ensure proper oscillator operation we recommend the following standard practices: - Keep traces as short as possible - Use a guard ring around the crystal Fig. 14 shows the recommended layout. Oscillator Layout
An external signal generator can be used to drive the divider chain of the V3020. Fig. 13a and 13b show how to connect the signal generator. The speed can be increased by increasing the signal generator frequency to a maximum of 128 kHz. An external signal generator and test modes can be combined. To leave test both test bits (address 0, bits 2 and 3) must be cleared by software. Test corrupts the current time and date and so the time and date should be reloaded after a test session. Signal Generator Connection
Fig. 14
Access Considerations The section "Communication Cycles" describes the serial data sequences necessary to complete a communication cycle. In common with all serial peripherals, the serial data sequences are not re-entrant, thus a high priority interrupt, or another software task, should not attempt to access the V3020 if it is already in the middle of a cycle. A semaphore (software flag) on access would allow the V3020 to be shared with other software tasks or interrupt routines. There is no time limit on the duration of a communication cycle and thus interrupt routines (which do not use the V3020) can be fully executed in mid cycles without any consequences for the V3020.
Fig. 13a
Note: The peak value of the signal provided by the signal generator should not exceed 1.5 V on XO.
Fig. 13b
Note: The peak value of the signal provided by the signal generator should not exceed 1.5 V on XO.
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V3020
Typical Applications
V3020 Interfaced with Intel CPU (RD/WR Pulse)
Fig. 15
V3020 Interfaced with Motorola CPU (Advanced R/W)
Fig. 16
3 Wire Serial Interface
1) 2)
With strobe low bits are written to the V3020, and with strobe high bits are read from the V3020 For serial ports with byte transfer only, an address command cycle should be combined with every data cycle to give 8 address bits and 8 data bits. For example to read the current minutes, write address data F + 2 (1111 + 0011) and then read 8 data bits.
Fig. 17
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V3020
Battery Switch Over Circuit a)
*
Use Schottky barrier diodes. The BAT85 has a typical VF of 250 mV at an IF of 1 mA. The reverse current is typically 200 nA at a VR of 5 V. The reverse, recovery time is 5 ns. For surface mount applications use the Philips BAT17 in SOT-23 or other.
Fig. 18
Ordering and Package Information
Dimensions of 8-Pin SOIC Package
D
C
E 0-8 L H
A1 B e
A
Dimensions in mm A A1 B C D E e H L Min. 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.40 Nom. 1.63 0.15 0.41 0.20 4.93 3.94 1.27 5.99 0.64 Max 1.75 0.25 0.51 0.25 5.00 4.00 6.20 1.27
4
3
2
1
5
6
7
8
Fig. 19
Dimensions of 8-Pin TSSOP Package
Fig. 20
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V3020
Ordering Information When ordering, please specify the complete Part Number Part Number V3020SO8B V3020SO8A -40C to +85C V3020TP8B V3020TP8A V3020XSO8B V3020XSO8A -40C to +125C V3020XTP8B V3020XTP8A 8-pin TSSOP 8-pin TSSOP Tape & Reel Stick 8-pin TSSOP 8-pin TSSOP 8-pin SOIC 8-pin SOIC Tape & Reel Stick Tape & Reel Stick Temperature Range Package 8-pin SOIC 8-pin SOIC Delivery Form Tape & Reel Stick Package Marking V3020 EM%## V3020 EM%## 3020 3020 V3020 EM%X## V3020 EM%X## 3020 X 3020 X
Where % and ## refer to the lot number and date (EM internal reference only).
EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of EM are granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for use as components in life support devices or systems.
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